AnalogBits Unveils Next-Gen Power Management IP for TSMC's N2P Process at 2026 Symposium

Gate News message, April 16 — AnalogBits, a subsidiary of South Korean design house SeemiFive, will showcase next-generation power management intellectual property (IP) solutions based on TSMC’s advanced N2P (2-nanometer) process at the TSMC 2026 Technology Symposium on April 22 in Santa Clara, California. The announcement was made on April 15.

The newly unveiled solutions include integrated On-die LDO (low-dropout regulator) with glitch detection and voltage droop sensing, pinless PVT sensors, and low-power PLL (phase-locked loop) offering real-time power monitoring. The pinless PVT sensor, debuted for the first time, achieves high accuracy of ±3.5°C, while the low-power PLL delivers ultra-low power consumption at 0.5 microwatts per MHz.

AnalogBits’ new IP addresses technical challenges faced by multi-kilowatt AI and high-performance computing (HPC) systems, which struggle with power density, thermal management, and performance variability issues. The solutions enable power-performance-area (PPA) optimization and intelligent on-chip power management on advanced SoCs. The company, which has shipped billions of IP cores across processes from 0.35 micrometers to 2 nanometers, plans to participate in subsequent TSMC technology symposiums in Taiwan, Europe, China, and Japan to expand global customer engagement.